ABSTRACT: Epilepsy is a prevalent neurological disorder affecting millions worldwide, in which people experience frequent seizures due to abnormal electrical activity in the brain. Early detection of structural brain changes associated with seizure conditions can enhance diagnosis and treatment planning. While Electroencephalography (EEG) is widely used for real-time seizure detection, Magnetic Resonance Imaging (MRI) provides structural information that can reveal abnormalities linked to seizure disorders. This paper proposes a novel framework for analyzing seizure-associated brain structural patterns in MRI images, combining Convolutional Neural Networks (CNN) with Horizontal Visibility Graph (HVG) construction and attention-based Graph Transformer classification. The preprocessing pipeline includes grayscale conversion, noise removal, and intensity normalization. Region-of-interest (ROI) signals are derived through spatial averaging of pixel intensities. These signals are converted to HVGs, where each data point becomes a node and edges are formed using horizontal visibility criteria. Graph-theoretic features—degree, clustering coefficient, and average shortest path length—are extracted to form a spatial structural feature set. An attention-based Graph Transformer classifier then performs binary classification into abnormal (seizure) and normal cases. The core innovation lies in a hybrid CNN + HVG + Graph Transformer architecture that jointly models spatial and structural properties of MRI data. It is important to note that the dataset uses tumor-affected MRI images as proxies for seizure-associated structural changes; while this is a recognized limitation, it allows exploration of the clinical hypothesis that tumor-induced structural alterations share characteristics with seizure-related atrophy. Experiments demonstrate an overall classification accuracy of 96.08%, a seizure class (Class 1) recall of 1.00, precision of 0.94, and F1-score of 0.97, outperforming traditional machine learning, CNN-only, RNN-based, and standard Graph Neural Network baselines. These results indicate that graph-based structural representation of MRI-derived signals can support neurological diagnosis with strong computational accuracy.
Keywords — Seizure-Associated Abnormalities, MRI, Visibility Graph, Horizontal Visibility Graph (HVG), CNN, Graph Transformer, Structural Representation, Deep Learning.

ABSTRACT: Replicated key-value stores sit at the core of many distributed applications, where they are expected to serve requests quickly, keep data safe, and keep working when individual machines fail. Building one is largely a question of how much consistency to trade away for availability and speed, and the answer gets harder once crashes and reconfiguration enter the picture. In this paper we describe a key-value store built around a modified chain replication protocol. It keeps data strongly consistent and durable, and stays available as long as a majority of the replicas are up. We cover the client-server protocol, how the system reacts to failures, and how state is stored on disk, and we measure the result under several workloads. Across different key and value sizes, client counts, and read-write mixes the system behaves predictably, and it stays correct when nodes go down.
Keywords: Distributed systems, Chain replication, Key-value store, Strong consistency, Fault tolerance, gRPC, Leader election, Replication chain, Durability, Availability.

ABSTRACT: Phishing websites are taking the form of multi-modal threats which integrate bad URLs, spam email messages, altered images, and hacked attachments hence rendering the traditional one-layered detection a futile exercise. This paper suggests a multi-mode phishing detection system with structural validation, machine learning, and generative AI. The system validates DNS and database before the classification is done using some engineered features of the URLs, email, files, and images which is then done by the random forest. Screenshot-based phishing uses OCR to improve contextual reading and minimize false positives, whereas generative AI can be used to improve the context of phishing. The system has an overall accuracy of 97% of detection modules and is implemented with MERN architecture and with secure APIs and a monitoring dashboard.
Keywords: Phishing Detection, Multi-Modal Security, Random Forest, Natural Language Processing, Optical Character Recognition (OCR), Generative Artificial Intelligence, DNS Validation, Cybersecurity Analytics, Threat Monitoring Dashboard.

ABSTRACT: Decimal computation/calculation playing a major role and gaining attention by scientists and analysts because of their significance in various human-centric applications. Executing these operations in hardware offers better speed than software methods. This is highly beneficial for systems that need quick responses. Decimal addition is most important and basic decimal operation among all remaining operations and also one of the essential one. The Complementary Metal Oxide Semiconductor (CMOS) technology has the benefit of decreasing the propagation delay in virtual systems. Decimal adders can be developed as Ripple Carry Addition (RCA) structure or as a Carry Look-Ahead Addition (CLA) structure with more rapid and extra hardware cost. This paper discusses the design and performance analysis of a Carry Look-Ahead Decimal Adder (CLDA) implemented using CMOS technology. This work developed CLDA design to mitigate the latency limitations of conventional Ripple Carry Decimal Adder (RCDA) by bettering carry propagation efficiency. The design is executed and simulated using 45nm and 90nm technologies, and key performance metrics such as delay, power consumption, PDP, EDP are evaluated. The results shows that the proposed CLDA achieves notable performance improvement over the conventional RCDA. In 45nm technology, the CLDA provides approximately 19.9% reduction in delay and 19.8% improvement in Power Delay Product (PDP), indicating enhanced speed and energy efficiency. In 90nm technology, a delay reduction of about 13.3% is observed, while PDP remains nearly comparable. The novelty of this work lies in the effective CMOS-based execution of CLDA and its comparative analysis across different technology nodes. These results confirm that the proposed CLDA is more suitable for high-speed arithmetic applications.
Keywords: CMOS technology, CLDA, RCDA, BCD adder, Decimal adder, PDP, EDP, Cadence virtuoso..

ABSTRACT: The threat posed by plant diseases to the global food supply is a persistent problem, causing yield and financial losses. For diagnostics, speed and accuracy are important, but traditional methods tend to be too reliant on manual inspections that are too slow, and too inconsistent to be useful for the farming communities that need them most. This paper describes an automated diagnosis method using transfer learning with the EfficientNet-B4 architecture. Training was done with the Medley Plant Disease dataset with over 100,000 labeled leaf images spanning 39 classes. Data augmentation and model generalization fine-tuning were performed for the final model to achieve a validation accuracy of 98.41% and a test accuracy of 97.02% model, demonstrating an emphasis on the robustness of the model to diverse types of diseases. This paper illustrates the use of deep learning with high accuracy to be deployed on a mobile and cloud-based with the potential for precision farming at scale and improved decision support for farmers.
Keywords— Plant disease detection, Deep learning, Transfer learning, EfficientNet-B4, Precision agriculture, CNN.

ABSTRACT: In this paper an optimized deep learning model has been proposed for automated Steel Surface Defect Detection [1] to mark the disadvantages of manual inspection methods and baseline object detection models. Steel surface has so many defects which can seriously attack safety and integrity of the product if it’s not detected early. The YOLO family models offer fast and reliable object detection [2], but their performance in the market is often restricted by many limitations. This Study revolves around YOLO V12 [3]. YOLO V12 [3] is a recent growth in object detection. The effectiveness for steel Surface Defect Detection compared to earlier YOLO baseline variants has not been widely evaluated. This study aims to explore the potential of YOLO V12 in this field. When the model is tested on the NEU Surface Defect Database, without any assumptions, the proposed model shows better detection accuracy, progressive stability, increased generalization ability with a mAP50 of 0.863. The presented model gives an efficient real time solution which is needed for industrial deployment and also having quality observation systems.
Keywords: Deep Learning, Steel Surface Defect Detection, YOLO, Transfer Learning.

ABSTRACT: Aquaculture is an important process in the world food security, but fish health management is a major challenge as bacterial diseases, viral diseases, fungal diseases, and parasitism are widespread. The conventional methods of diagnostics depend rather on the manual checking of the specialists, which leads to subjective diagnostics, slowness of the intervention, and inability to make the interventions in large or distant farms. To resolve these issues, an AI-based Fish Disease Detection System was built based on a database of fish images taken in aquaculture farms and open repositories in 2020-2024 and comprised more than 45 disease types of both freshwater and marine organisms. The preprocessing image pipeline is using the OpenCV-based resizing, normalization, bilateral filters, and contrast enhancement to standardize visual inputs and enhance features in the visual image. The identification of the disease combines a deep learning layer based on MobileNetV2 which is used to classify the disease, Gemini Vision AI which is an advanced multimodal reasoning tool, and a rule-based fallback system to remain reliable in situations of low confidence. White spots, lesions, texture variation and fin ruinous are key visual attributes that are extracted to aid in the effective learning of features. The system produces real-time, high-accurate diagnosis, which gives the disease severity, recommendations to take, as well as prevention guidelines. This intelligent diagnostic framework would boost the accuracy of detection through the combination of deep learning, computer vision, and rule-based reasoning, help decrease fish mortality, and encourage sustainable practices in the aquaculture industry.
Keywords: Fish Disease Detection, Aquaculture, Deep Learning, Computer Vision, Image Processing, Real-Time Diagnostics”.

ABSTRACT: The Wireless Sensor Networks (WSNs) is a kind of ad-hoc network of interconnected sensors to observe surrounding environment and record real-time values as the environment changes from time to time. The main source of the power supply for sensors in WSNs is power-constrained batteries built into sensors, which significantly affects the WSN lifetime. The uneven geographical structure causes multiple random paths to be followed in data collection. However, due to constrained battery power capacity and ecological variations, power utilization is a tricky issue in WSN. The work done in this paper proposes an efficient data collection mechanism in Mobile Sink WSN using reinforcement learning in order to address battery power constrain in WSN. The proposed model uses Q-Learning approach that induces automatic learning through the shortest path for data collection. The outcomes of the proposed model’s experiment show it works much better as compared to the existing model.
Keywords: Keywords: WSN, Q-Learning, Mobile Sink, Reinforcement Learning.

ABSTRACT: Lithium Batteries are the powerhouses of modern electric vehicles (EVs). The measurement of the battery’s state of charge (SOC) data is crucial to planning for long-distance travel and the breaks required to charge in between. In real life, the sensor data can be prone to external noise and thus the correct SOC may not be displayed accurately. To avoid this, the current manuscript proposes a multimodal neural network and sensor-based SOC prediction for long-distance EV travel plans. The proposed model is trained from real-world battery behavior on parameters such as charging/discharging trends, distance covered and environmental factors that affect the battery SOC. The proposed model learns battery discharge patterns affected by various load scenarios, making the system robust. Furthermore, this can be used for prediction based on the sensor, environmental and load conditions. The proposed technology can be extended to other applications such as drones, delivery robots, and e-bikes for optimizing efficiency, safety and route optimization.
Keywords—Battery life prediction, multimodal neural network, sensor based battery life, baseline neural network and Adaptive neural network.

ABSTRACT: Energy-efficient D latch design is crucial for low-power VLSI applications, as latches form the core of sequential circuits and memory elements. This paper presents the design and comparative analysis of 7T, 6T, and 5T D latches optimized for low-power operation. The designs are implemented and simulated using Cadence Virtuoso in 45 nm CMOS technology with a supply voltage of 1V. The performance is analyzed based on power dissipation, propagation delay, and Power delay product. Compared to the 6T D-latch, it is observed in 7T D-Latch that there is -99.9978% reduction in power dissipation and increase in delay by 17.704%. Similarly, when compared to the 6T D-latch, it is observed in 5T D-latch that there is -99.9973% reduction in power dissipation and increase in delay by 16.704%. Also, a 4-bit Serial-In Serial-Out (SISO) shift register is implemented using the D latch designs. The shift register performance is analyzed in terms of power, delay, and PDP. Results indicate that the 5T latch-based shift register achieves the minimum PDP of 95.3 × 10⁻¹⁹, making it highly suitable for low-power VLSI applications.
Keywords—VLSI, Low-Power Design, Energy-Efficient Circuits, D Latch, Shift Register, Cadence Virtuoso, Power–Delay Product.

ABSTRACT: Power consumption is a critical concern in contemporary Very Large-Scale Integration (VLSI) systems owing to increasing demand for energy-efficient electronic devices. Reducing power while maintaining system performance is an important objective in digital circuit design. This paper describes the design and low-power optimization of an elevator controller based on Finite State Machine (FSM) implemented in the Register Transfer Level (RTL). The controller manages elevator operations such as floor requests, movement, and emergency stop using a structured FSM architecture. The suggested design uses various low-power methods, such as power-aware state encoding with gray code and gray encoding with clock gating to lower the total amount of dynamic power used. The Xilinx Vivado suite is used to construct the suggested design in Verilog. According to empirical analysis, every method helps to lower dynamic power. In comparison to the baseline design, the improved design reduces total on-chip power by 36.69 % and dynamic power by 39.0 %. The findings show that the power efficiency of FSM-based elevator controller systems may be enhanced by combining several low-power strategies while maintaining functionality.
Keywords: State encoding, Elevator controller, Low-power VLSI architecture, Clock gating, Finite state machines.

ABSTRACT: This paper describes the detailed performance study of a low power, single ended 7T SRAM cell across various technological nodes of 45nm, 32nm, and 22nm. The best result of power dissipation is obtained at the technology node of the 32 nm process for this SRAM cell, where the powers of Write 1, Write 0, Read 1, and Read 0 operations are measured as 0.4523 (µW), 0.778 (µW), 0.259 (µW), and 0.418 (µW), respectively. Additionally, this cell shows better delay performance at the technology node of the 32 nm process, where the Write1, Write0, and Read0 delay times are measured as 18.13 ps, 14.7 ps, and 15.6 ps, respectively, to enable the memory access process faster. Moreover, the single ended 7T SRAM cell shows the highest noise margin at the technology node of the 32 nm process compared to the other two processes, where the highest noise margin value measured at the technology node of the process is 0.32807 V, as opposed to values of 0.30184 V and 0.26861 V at the technology nodes of the other two processes, respectively.
Keywords: Single ended, SRAM, HSNM, low power.

ABSTRACT: Reliable perception capabilities are essential for assistive navigation systems for the visually impaired, which must operate within the constraints of computing and energy limits of edge devices. On low-power embedded platforms, the proposed study aims to implement an object identification framework that is based on edge optimization of transformers. This framework would allow for real-time navigation aid. This study proposes an architecture that efficiently captures local characteristics and global contextual information by integrating a reduced transformer encoder with a lightweight convolutional backbone. Structured pruning and low-precision inference are examples of model-level optimization that drastically cut down on memory usage and computational overhead, allowing for steady real-time performance. To improve domain relevance, training was carried out utilizing a two-stage approach that mixed a task-specific assistive navigation dataset with large-scale benchmark data (MS COCO dataset). Further enhancement in visual conditions, a multimodal sensing using ultrasonic distance estimation is needed to include. The final result of the work shows the optimized transformer framework with good comparison between the latency, detection accuracy, and resource consumption, which shows a suitable model for deployment on the continuous edge. Moreover, considering efficiency aware transformer models shows scalable assisted navigation systems which also boosts autonomous movement.
Keywords: Edge Computing, Transformer-Based Object Detection, Assistive Navigation, Real-Time Inference, Embedded Systems.

ABSTRACT: In this work, a smart vacuum cleaning robot based on Arduino Uno microcontroller with an aim of achieving efficient, low cost and autonomous cleaning of floor is studied. The designed system was combination of ultrasonic sensors, which is used to detect the presence of the obstacles, the motor drivers which are used to control the navigation system, and the suction mechanism which is used to remove the dust. The algorithm on which the robot was built features a preprogrammed moving, allowing to move in a system herself without colliding, thus performs optimally in the area coverage. The hardware architecture was adjusted with caution to maintain a balance between the efficiency of the performance and the energy consumption of the hardware and the embedded C programming was used to implement the software logic in the arduino actual IDE environment. The system architecture depicted a smooth flow of interaction between sensing, processing and actuation units. The cleaning efficiency, navigation accuracy and obstacle avoidance capabilities were calculated by experimental testing in the held indoor environments. The results demonstrated that the suggested robot is reasonable outcomes in relation to improved cleaning space as well as restricted hand control compared to conventional cleaning plans. Besides this, the system has been found out to be cost effective, scalable and hence suitable in both the domestic and small scale industry. The research will have an impact on creating easy implementation automation solution and other possible bright opportunities of microcontroller robotics in daily life.
Keywords- Arduino Uno, Vacuum Cleaning Robot, Autonomous Navigation, Ultrasonic Sensor, Embedded Systems, Robotics Automation.

ABSTRACT: This paper presents a novel hybrid image captioning architecture named DCAT (Dual CNN Attention Transformer) that eliminates major drawbacks of CNN-LSTM approaches. The method uses two distinct pre-trained CNNs, DenseNet201 and InceptionV3, working simultaneously as dual encoders. Their output feature vectors (1920-dim and 2048-dim, respectively) are combined by concatenation to create a 3968-dimensional rich fused representation. The fused vector is further divided into four learnable soft visual tokens, which are used as key-value context for a cross-attention transformer decoder. This change removes the sequential LSTM bottleneck in previous methods. A single transformer decoder block has masked multi-head self-attention, cross-attention to soft visual tokens, position-wise feed-forward network, residual connections, and layer normalisation. The training criterion is masked sparse categorical cross-entropy, ignoring padding positions. At inference time, beam search is used for decoding. When tested on the Flickr8k dataset, DCAT achieves BLEU-1: 0.5505, BLEU-2: 0.3643, BLEU-3: 0.2395, and BLEU-4:0.1504, significantly outperforming the Dense Net201+LSTM baseline by 36.7% in terms of BLEU-4 and beating all other CNN+LSTM models. Such findings illustrate that fusing complementary dual CNN encoders and a cross-attention transformer decoder yields very accurate and well-interpreted image captions.
Keywords- image captioning, dual CNN encoder, DenseNet201, InceptionV3, transformer decoder, cross-attention, soft visual tokens, BLEU score, Flickr8k, multimodal deep learning, natural language processing.

ABSTRACT: The demand to spare energy while creating efficient Very Large Scale Integration (VLSI) systems continues to increase due to the rise in use of portable devices like cell phones that access Internet of Things (IoT). This means that there is a need for designing a low-power computation unit. As a main component of digital processors, Arithmetic Logic Units (ALU) account for a major portion of system power consumption because they operate continuously throughout their operational life cycle. In addition to those reasons, this study proposed an energy efficient ALU as an example of an adaptive clock gating based on reducing switching activity that is not needed, therefore minimizing the amount of dynamic power consumption. The proposed design is developed in Verilog HDL at Register Transfer Level (RTL) and evaluated using standard Electronic Design Automation (EDA) tools via simulation. The fine grained adaptive clock gating concept allows for selective activation of ALU modules where operational requirement dictates. Performance metrics include power, delay, Power Delay Product (PDP), and energy measurements. Based on our results, the proposed adaptive ALU reduces the power from 52.30 µW to 24.10 µW for a 53.92% reduction of power, while the PDP has decreased from 109.83 pJ to 55.43 pJ. The delay increased slightly from 2.10 ns to 2.30 ns, however, the overall energy efficiency increased considerably demonstrating the effectiveness of the proposed solution.
Keywords— Adaptive Clock Gating, Low-Power VLSI Design, Arithmetic Logic Unit (ALU), Power Delay Product (PDP), Energy-Efficient Architectures.

ABSTRACT: The need for optimized arithmetic units has been underscored by the escalating demand for high-speed and energy-efficient digital systems, particularly in the design of Arithmetic Logic Units (ALUs). This study presented a high-speed and low-power Vedic multiplier using an enhanced adder structure suitable for next-generation ALU applications. The proposed design is based on the Urdhva Tiryakbhyam algorithm, which allows parallel generation of partial products and thus reduces computational delay. A modular Vedic multiplier architecture is realized and merged with a hybrid enhanced adder to minimize carry propagation delay as well as switching activity. The entire design is described using Verilog HDL and synthesized in Xilinx Vivado for performance evaluation. Results show that the proposed design attains a delay of 24.8 ns at an operating power of 190 mW, which is better than conventional multipliers by about 45% in delay, 40% in power consumption, and up to 67% improvement in Power Delay Product (PDP). The enhanced hybrid adder reduces this further to 6.1 ns with lower power consumption; hence such an architecture becomes more appropriate when looking for high-performance energy-efficient ALU systems.
Keywords— Vedic Multiplier, Urdhva Tiryakbhyam, Enhanced Adder Structure, Low Power VLSI Design, Arithmetic Logic Unit (ALU).

ABSTRACT: As VLSI systems continue to grow in complexity, there is increasing demand for verification methodologies that are both efficient and scalable. Functional verification of widely used communication protocols, such as I2C and SPI, is particularly problematic because traditional verification methods often do not provide complete coverage or identify defects or errors early during the design phase. This delay in identifying defects or errors leads to an increase in the overall time and cost of the manufacturing process. This work presented a Coverage Driven Verification (CDV) and Assertion Based Verification (ABV) methodology that combined Constrained Random and Directed Testing, System Verilog assertions, and functional coverage models to provide a comprehensive verification process for VLSI systems. A reusable testbench environment based on the Universal Verification Methodology (UVM) is developed to provide verification of the functionality of the protocol, the timing constraints associated with the protocol, and corner case scenarios. The proposed CDV/ABV methodology achieved 98.75% functional coverage, 97.90% code coverage and 100% assertion coverage. Through fault injection analysis, a 100% detection rate for all fault conditions was achieved, while regression testing produced a 98.33% efficiency rating. In addition, the simulation time was reduced from 120 minutes to 85 minutes, which has improved the overall verification efficiency. The results demonstrated that the proposed methodology improves reliability, scalability and performance in the verification of VLSI systems.
Keywords— Coverage-Driven Verification (CDV), Assertion-Based Verification (ABV), System Verilog, Universal Verification Methodology (UVM), I2C and SPI Protocols.

ABSTRACT: For the authors, the fast development of online learning requires new solutions instead of conventional Learning Management Systems (LMS). This research paper is a report about an AI-powered Progressive Web Application (PWA) that will help to optimize the online learning experience by making them more accessible, personalized, and intelligent. The combination of the functionality of PWAs and Artificial Intelligence allows the system to support offline interactions, be compatible across platforms, and provide users with real-time impressions with the push messages. The suggested application uses the latest technologies like React.js, Node.js, Firebase, and the Gemini API to provide voice-based search and AI-based content suggestions. The system utilizes machine learning modalities to study user behavior and dynamically adjusts an educational content which adapts with the personal preferences and learning tendencies. Also, voice-enable search capability enhances usability since users can call the information with the highest possible efficiency without having to use any text-based query. An end user testing of the system shows that learning accessibility and engagement have improved significantly. The findings show that AI implementation combined with the method of PWA technology improves the user experience, stimulates continuous interaction, and increases the desire to read educational materials. Moreover, the system has a high accuracy level when it comes to voice query response, which confirms its efficiency in the role of an intelligent learning assistant.
Keywords— Artificial Intelligence, Progressive Web Application (PWA), Voiced Based Searching, E-Learning

ABSTRACT: An efficient bug tracking solution gives all members of the software development team (testers, coders, managers, administrators, etc.) a means to locate, submit, distribute and solve software bugs quickly and accurately. The purpose of this bug tracking solution is to provide a quick, accurate and reliable means for these individuals to work together with each other. The design of the bug tracking solution is based upon an established process for reporting bugs, secure user logins, and the ability to view real-time status updates of both software bugs and bug reports. Please note that the two primary views of the software for the bug tracking solution are: The back-end (software logic), and the end-user's experience managing and tracking bugs in the solution. The back-end logic of the solution is designed using Object-Oriented Programming (OOP), allowing for the creation of reusable, modular components and customized to each user-type. When a user (any user type) submits the status of their bug report, the user's request will first check that enough information on the bug being reported exists, that it has been validated as correct, and that this information can be stored in a manner that can track that bug in the future. Additionally, the bug tracking solution allows the insertion of bug severity and bug urgency levels, which enables users to determine how they should proceed in resolving a bug. In the user face thing, a Java Swing based GUI that gives users a place thats pretty easy to use. Where, users can put in bugs, update how far along they are, look over what they've been given to do, and take care of system data. Future stuff to hook it up with MySQL will make sure the data is safe, and Maven project management will help it grow and handle what it needs to work. These parts work together, to make a user-friendly tool that is definitely going to improve software quality and help the teams work together better.
Keywords: Bug Tracking System, Java Swing, Defect Management, Role-Based Access Control, Software Quality Assurance.

ABSTRACT: A majority of experts agree that THz (terahertz) communication will be a primary enabler for 6G (sixth generation) wireless networks due to both its ample spectrum resources and enormous capacity potential. Nevertheless, reliable performance evaluations of THz systems require precise modelling of both channel fading and phase-based uncertainties. In general, traditional methods for deriving symbol error rates (SERs) assume either that there is perfect phase alignment or use simple approximations that ignore the statistical fluctuations of phase. Recent studies have found that including a probability density function of the phase jitter into the derivation of the SER results in substantially better analytical accuracy and more reliable predictions. In this paper, a general theoretical analysis of phase-jitter-based SER modelling for THz and mixed THz/RF communication systems will be outlined. This effort adds to the analytical framework presented by [1], extends the previous modelling to include THz-related issues, and provides a general discussion on phase-aware detection, enhanced statistical reliability by making use of phase-based measures, and performance scaling with respect to the SNR (signal-to-noise ratio). Additionally, we will include comparison tables illustrating that the use of phase-jitter-based modelling provides a consistent SER improvement over traditional methods. Results indicate that incorporating statistical phase-aware modelling will yield improved analytical accuracy, enable a lower SNR to meet target reliability levels, and provide a basis for optimising future 6G networks.
Keywords: Terahertz communication, Phase Jitter, SNR, SER.

ABSTRACT: In this paper, the author has suggested a contactless toll collection system, which employs Artificial Intelligence (AI) and Number Plate Recognition (NPR) to enhance efficiency at the toll plazas. The system will be constructed under Raspberry Pi with a USB camera which will capture pictures of the vehicles in real time. A deep learning model based on the YOLO system detects the license plates and the vehicle numbers are recognized through the Optical Character Recognition (OCR). A sensor in the ultrasonic mode detects the coming vehicles and the automatic toll processing and the opening of the gates with the help of a DC motor and a driver. A database stores vehicle-related information and account balances, and the deduction of tolls can be done automatically. Status of transactions is displayed on an LCD screen, and a buzzer is used to notify the user about any errors or confirmations. Experimental findings indicate that the system is reliable to use, highly accurate and lessens congestion, delays and manual work, which is very economical as compared to traditional method of collecting tolls.
Keywords: Number Plate Recognition, YOLO, OCR, Raspberry Pi, Automated Toll System.

ABSTRACT: The prediction of time-series is a pillar of intelligent systems used in areas like energy, finance, medicine, and industrial Internet of Things; accurate predictions are the foundations of automated decision-making, effective resource distribution, and sound mechanisms of identifying anomalies. Archaeologies, such as recurrent neural networks (RNNs), long short-term memory (LSTM) networks, temporal convolutional network (TCNs), and Transformers, have significantly surpassed classical statistical models like ARIMA and exponential smoothing models in terms of precision in prediction since the emergence of deep learning. However, the natural incomprehensibility of such deep models the so-called black-box problem limits their application in safety-critical fields where regulatory standards, human trust and explainability cannot be compromised. The presented review is an overview of recent developments in the intersection of deep time-series forecasting and explainable artificial intelligence (XAI) along with a specific focus on their application to intelligent systems. We provide a taxonomy of deep forecasting architectures which includes RNN based, CNN/TCN based, Transformer based, hybrid and emergent foundation models. We then summarize a systematic review of XAI methods specific to time-varying data comprising feature attribution, time-sensitive saliency maps, attention-based explanations and intrinsically explainable architectures. Healthcare, energy, and industrial IoT Our synthesis will represent a more general finance, healthcare, energy, and industrial IoT, demonstrating how explanations assist in model debugging, building trust in a model, and human-AI collaboration. Among the open challenges that we address and discourse include scaling XAI to multivariate high-frequency data streams, standardizing measures of quality of explanations, and incorporating domain knowledge into pipelines in forecasting
Keywords: smart systems, time series prediction, deep learning, explainable AI, XAI, attention, Transformers, feature attribution, anomaly detection.

ABSTRACT: Human communication is inherently multimodal, relying on a complex interplay between facial expressions and vocal prosody. However, traditional Affective Computing systems often rely on unimodal analysis—typically visual—which renders them susceptible to error when subjects mask their true emotions (e.g., a "social smile" concealing anxiety). To address this limitation, this paper proposes a real-time Multimodal Emotion Perception System that integrates visual and acoustic cues using a sequential asynchronous pipeline. The architecture leverages DeepFace (VGG-Face) for facial feature extraction and a fine-tuned Wav2Vec2 Transformer for speech sentiment analysis. The Multimodal Congruence Index (MCI) is a new decision level fusion algorithm that is used to measure the semantic agreement between modalities. The results of the experiment prove that unimodal accuracy varies in noisy conditions, whereas the proposed fusion model manages to detect emotional conflict with accuracy 88% correct, which is a strong solution to behavioral analysis and detecting lies in the interview context.
Keywords: Multimodal Fusion, Affective Computing, DeepFace, Wav2Vec2, Congruence Index, Human-Computer Interaction.